PKUIR Community: Interdiscipline - bob登陆网站 http://hdl.handle.net/20.500.11897/8 Interdiscipline 2025-03-14T20:48:06Z PrivLM-Bench: A Multi-level Privacy Evaluation Benchmark for Language Models http://hdl.handle.net/20.500.11897/739767 Title: PrivLM-Bench: A Multi-level Privacy Evaluation Benchmark for Language Models Authors: Li, Haoran; Guo, Dadi; Li, Donghao; Fan, Wei; Hu, Qi; Liu, Xin; Chan, Chunkit; Yao, Duanyi; Yao, Yuan; Song, Yangqiu Abstract: The rapid development of language models (LMs) brings unprecedented accessibility and usage for both models and users. On the one hand, powerful LMs achieve state-of-the-art performance over numerous downstream NLP tasks. On the other hand, more and more attention is paid to unrestricted model accesses that may bring malicious privacy risks of data leakage. To address these issues, many recent works propose privacy-preserving language models (PPLMs) with differential privacy (DP). Unfortunately, different DP implementations make it challenging for a fair comparison among existing PPLMs. In this paper, we present PrivLM-Bench, a multi-perspective privacy evaluation benchmark to empirically and intuitively quantify the privacy leakage of LMs. Instead of only reporting DP parameters, PrivLM-Bench sheds light on the neglected inference data privacy during actual usage. PrivLM-Bench first clearly defines multifaceted privacy objectives. Then, PrivLMBench constructs a unified pipeline to perform private fine-tuning. Lastly, PrivLM-Bench performs existing privacy attacks on LMs with pre-defined privacy objectives as the empirical evaluation results. The empirical attack results are used to fairly and intuitively evaluate the privacy leakage of various PPLMs. We conduct extensive experiments on three datasets of GLUE for mainstream LMs.(1) 2024-01-01T00:00:00Z Precise <i>p</i>-type and <i>n</i>-type doping of two-dimensional semiconductors for monolithic integrated circuits http://hdl.handle.net/20.500.11897/739765 Title: Precise <i>p</i>-type and <i>n</i>-type doping of two-dimensional semiconductors for monolithic integrated circuits Authors: Pan, Yu; Jian, Tao; Gu, Pingfan; Song, Yiwen; Wang, Qi; Han, Bo; Ran, Yuqia; Pan, Zemin; Li, Yanping; Xu, Wanjin; Gao, Peng; Zhang, Chendong; He, Jun; Xu, Xiaolong; Ye, Yu Abstract: The controllable fabrication of patterned p-type and n-type channels with precise doping control presents a significant challenge, impeding the realization of complementary metal-oxide-semiconductor (CMOS) logic using a single van der Waals material. However, such an achievement could offer substantial benefits by enabling continued transistor scaling and unprecedented interlayer interconnect technologies. In this study, we devise a precise method for two-dimensional (2D) semiconductor substitutional doping, which allows for the production of wafer-scale 2H-MoTe2 thin films with specific p-type or n-type doping. Notably, we extend this approach to the synthesis of spatially selective doped 2H-MoTe2 thin films via a one-step growth method, facilitating the monolithic integration of p-type and n-type semiconductor channels. Leveraging this advancement, we successfully fabricate a chip-sized 2D CMOS inverter array that demonstrates excellent device performance and yield. Collectively, these findings represent a significant stride towards the practical incorporation of 2D semiconductors in very large-scale integration technology. The fabrication of n- and p-type semiconducting channels based on the same layered material would simplify the implementation of 2D electronics. Here, the authors report a spatially selective doping method for the synthesis of wafer-scale p- and n-type 2H-MoTe2 thin films, and their application for the realization of complementary 2D transistor and inverter arrays. 2024-11-07T00:00:00Z 中国粮食主产区农业发展空间格局与差异化发展 http://hdl.handle.net/20.500.11897/739545 Title: 中国粮食主产区农业发展空间格局与差异化发展 Authors: 马楠; 高原; 沈体雁 Abstract: 明晰粮食主产区农业分布空间格局,基于分区特征推动农业差异化发展具有重要理论和实践意义。文章基于2012—2021年粮食主产区所含县域单元农业发展相关数据,从效率性和公平性视角切入,探讨了中国粮食主产区的分区及差异化发展路径。结果表明:(1)粮食主产区农业发展的核心区位于由土地资源禀赋、生产技术要素投入、商品粮供给能力三类标准差椭圆合围的138个市域所辖的1126个县域内,其中心位于河南濮阳南乐县等地形成的三角地带。(2)粮食主产核心区农业发展市场空间格局呈现出十分明显的圈层特征,其中空间邻近性最强的50%圈层城市聚集在以安徽六安霍邱县等地所合围的“O”型结构区域内。(3)农业发展和农业人口的网络轴线呈“东北—西南”向分布,且存在以河北廊坊广阳区等为端点的“纺锤体”分离地带。进一步分析,可将粮食主产区划分为“三类五区”:最优/次优效率发展区、最优/次优公平发展区、最优平衡发展区。(4)效率发展区、公平发展区和平衡发展区,分别以机械化等现代要素投入、产业链延伸以及劳动力等传统要素投入等为抓手推动农业发展;依托交通运输网络、农业经济联系等多元渠道可以实现县域农业协同发展。; 明晰粮食主产区农业分布空间格局,基于分区特征推动农业差异化发展具有重要理论和实践意义。文章基于2012—2021年粮食主产区所含县域单元农业发展相关数据,从效率性和公平性视角切入,探讨了中国粮食主产区的分区及差异化发展路径。结果表明:(1)粮食主产区农业发展的核心区位于由土地资源禀赋、生产技术要素投入、商品粮供给能力三类标准差椭圆合围的138个市域所辖的1126个县域内,其中心位于河南濮阳南乐县等地形成的三角地带。(2)粮食主产核心区农业发展市场空间格局呈现出十分明显的圈层特征,其中空间邻近性最强的50%圈层城市聚集在以安徽六安霍邱县等地所合围的“O”型结构区域内。(3)农业发展和农业人口的网络轴线呈“东北—西南”向分布,且存在以河北廊坊广阳区等为端点的“纺锤体”分离地带。进一步分析,可将粮食主产区划分为“三类五区”:最优/次优效率发展区、最优/次优公平发展区、最优平衡发展区。(4)效率发展区、公平发展区和平衡发展区,分别以机械化等现代要素投入、产业链延伸以及劳动力等传统要素投入等为抓手推动农业发展;依托交通运输网络、农业经济联系等多元渠道可以实现县域农业协同发展。 2025-01-26T00:00:00Z The Maximum Storage Capacity of Open-Loop Written RRAM is Around 4 Bits http://hdl.handle.net/20.500.11897/739425 Title: The Maximum Storage Capacity of Open-Loop Written RRAM is Around 4 Bits Authors: Li,Yongxiang; Wang,Shiqing; Sun,Zhong Abstract: <div data-language="eng" data-ev-field="abstract">There have been a plethora of research on multilevel memory devices, where the resistive random-access memory (RRAM) is a prominent example. Although it is easy to write an RRAM device into multiple (even quasi-continuous) states, it suffers from the inherent variations that should limit the storage capacity, especially in the open-loop writing scenario. There have been many experimental results in this regard, however, it lacks a comprehensive analysis of the valid multi-bit storage capability, especially in theoretical terms. The absence of such an insight usually results in misleading conclusions that either exaggerate or underestimate the storage capacity of RRAM devices. Here, by the concept of information theory, we present a model for evaluating the storage capacity of open-loop written RRAM. Based on the experimental results in the literature and the test results of our own devices, we have carefully examined the effects of number of predefined levels, conductance variation, and conductance range, on the storage capacity. The analysis leads to a conclusion that the maximum capacity of RRAM devices is around 4 bits.<br/></div> ?? 2024 IEEE. 2024-01-01T00:00:00Z